PCIe lane weirdness with inference loads: what are you seeing?

[sanevault]

Thought I'd post a small recipe because a lot of threads ask similar things.

This isn't revolutionary, but the combination of LM Studio and B200 felt surprisingly usable once I tuned around long context.

Maybe useful as a starting point for newer folks.

This is mostly for local work rather than public serving.

[rocmriley]

Maybe, but I had the opposite result. The reported numbers can look compelling, but in ordinary usage I didn't see the same benefit. Not saying you're wrong, just that I wouldn't lock that in as the lesson yet.

[vrambandit]

worth checking the driver first.

[turbogrid11]

A couple things I'd check first. Before rebuilding anything, I'd test one clean baseline with Llama and compare from there.

[signaltrack44]

A couple things I'd check first. Before rebuilding anything, I'd test one clean baseline with Llama and compare from there.

My first guess would be this: Before rebuilding anything, I'd test one clean baseline with Mixtral and compare from there. A lot of these threads end up being one bad config plus a pile of conclusions drawn from it.

[circuitwire58]

Did a small comparison this afternoon. On A6000 with MLX, I saw basically the same behavior. The surprise was that memory pressure showed up before throughput collapsed.

[cudapoint]

I'd approach it in a boring order. Before rebuilding anything, I'd test one clean baseline with Phi and compare from there. Once you know the plain path works, then add the faster path back in piece by piece.

[sanevault]

Thanks, that helps. I don't think your conclusion is far off. The biggest change for me was simplifying the stack instead of adding one more optimization layer.