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Posting this in case it saves someone else a little time.
I'm not trying to build a perfect architecture diagram. I just want a sane starting point around vLLM and 5090.
I'm especially interested in mistakes worth avoiding.
trying not to rebuild again
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Good point. The pattern around tail latency has been pretty similar for me.
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that fixed it for me too.
learning in public
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That matches what I was seeing. I don't think your conclusion is far off. I got better results once I stopped chasing one metric and just looked at whether the workflow felt usable.
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Maybe, but I had the opposite result. I wouldn't optimize around that first. On my side the bigger swing came from the runtime and not the model.
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I'd start with the simpler stack.
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I'd approach it in a boring order. If you're on PyTorch, I'd confirm the version first and then reduce variables until the behavior is obvious.
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Need a little more detail here. Are you testing this on 4090 or something else?
small models can still be useful
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Thanks, that helps. That matches what I saw on GB200.