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Posting this in case it saves someone else a little time.
I'm not trying to build a perfect architecture diagram. I just want a sane starting point around vLLM and M3 Max.
Would rather learn from your scars than collect my own all at once.
This is mostly for local work rather than public serving.
Apple Silicon • MLX mostly
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Good point. The pattern around NVFP4 has been pretty similar for me. Worth rechecking your defaults though, because one bad assumption can make the rest of the thread look confusing.
trying not to rebuild again
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A couple things I'd check first. Before rebuilding anything, I'd test one clean baseline with Mixtral and compare from there. Once you know the plain path works, then add the faster path back in piece by piece.
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I think the bottleneck is somewhere else. I get why that seems right, but on 5090 the bottleneck felt elsewhere. Could be a workload difference, but I wouldn't generalize too fast from one setup.
rack in the garage • local models everywhere
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A couple things I'd check first. Start by verifying the driver/runtime combo, then test with a smaller prompt, then look at long context.
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Tried to reproduce it just now. My result was mixed: first run looked bad, second run looked normal. The surprise was that memory pressure showed up before throughput collapsed.
small models can still be good
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Maybe, but I had the opposite result. I've seen people blame prefix caching when the real issue was much more mundane. Could be a workload difference, but I wouldn't generalize too fast from one setup.