PCIe lane weirdness with inference loads

[turboyard94]

I'd approach it in a boring order. Before rebuilding anything, I'd test one clean baseline with FLUX and compare from there.

What worked for me was pretty simple. On M3 Max, the easiest win is often to back off the aggressive settings and see whether the problem survives. Not glamorous advice, but repeatable baselines save a lot of time.

[thetarunner]

Thanks, that helps. That matches what I saw on B200. I got better results once I stopped chasing one metric and just looked at whether the workflow felt usable.

There are a few different conversations hiding inside this thread, so being explicit about the goal helps.

[vrambandit]

Thanks, that helps. I ended up in about the same place using PyTorch. Worth rechecking your defaults though, because one bad assumption can make the rest of the thread look confusing.

[signaltrack44]

Interesting, I hadn't tried that. The pattern around prefix caching has been pretty similar for me. The biggest change for me was simplifying the stack instead of adding one more optimization layer.