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+--- Thread: PCIe lane weirdness with inference loads (/showthread.php?tid=1070)
PCIe lane weirdness with inference loads - audiorunner74 - 10-11-2026
Posting this in case it saves someone else a little time.
I'm not trying to build a perfect architecture diagram. I just want a sane starting point around TensorRT-LLM and Threadripper box.
I'm especially interested in mistakes worth avoiding.
I care more about stability than squeezing the last possible tokens/sec out of it.