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+--- Thread: PCIe lane weirdness with inference loads: early impressions (/showthread.php?tid=962)
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PCIe lane weirdness with inference loads: early impressions - turboyard94 - 10-10-2026
Thought I'd post a small recipe because a lot of threads ask similar things.
This isn't revolutionary, but the combination of PyTorch and mini PC felt surprisingly usable once I tuned around tail latency.
Feel free to tear it apart if you see something dumb.
This is mostly for local work rather than public serving.
Re: PCIe lane weirdness with inference loads: early impressions - orbitbench6 - 10-11-2026
Quote:Thought I'd post a small recipe because a lot of threads ask similar things.
I don't think that's the whole story. I wouldn't optimize around that first. On my side the bigger swing came from the runtime and not the model. Not saying you're wrong, just that I wouldn't lock that in as the lesson yet.
Re: PCIe lane weirdness with inference loads: early impressions - cudapoint - 10-14-2026
That matches what I was seeing. I ended up in about the same place using LM Studio. Worth rechecking your defaults though, because one bad assumption can make the rest of the thread look confusing.
Re: PCIe lane weirdness with inference loads: early impressions - rocmriley - 10-15-2026
I'd approach it in a boring order. Start by verifying the driver/runtime combo, then test with a smaller prompt, then look at HBM constraints. A lot of these threads end up being one bad config plus a pile of conclusions drawn from it.
Re: PCIe lane weirdness with inference loads: early impressions - dockkite69 - 10-15-2026
A couple things I'd check first. If you're on vLLM, I'd confirm the version first and then reduce variables until the behavior is obvious. Once you know the plain path works, then add the faster path back in piece by piece.
Re: PCIe lane weirdness with inference loads: early impressions - signaltrack44 - 10-15-2026
My first guess would be this: On Threadripper box, the easiest win is often to back off the aggressive settings and see whether the problem survives. Not glamorous advice, but repeatable baselines save a lot of time.
Re: PCIe lane weirdness with inference loads: early impressions - turbogrid11 - 10-15-2026
that fixed it for me too.
Re: PCIe lane weirdness with inference loads: early impressions - batchwire - 10-15-2026
I'd approach it in a boring order. Before rebuilding anything, I'd test one clean baseline with Llama and compare from there.
Re: PCIe lane weirdness with inference loads: early impressions - vrambandit - 10-16-2026
worth checking the driver first. At this point the real bottleneck is my patience.
Re: PCIe lane weirdness with inference loads: early impressions - southtinker - 10-16-2026
A couple things I'd check first. If you're on PyTorch, I'd confirm the version first and then reduce variables until the behavior is obvious. Once you know the plain path works, then add the faster path back in piece by piece.